1. Field of the Invention
The present invention relates to a reverse level shift circuit for converting a voltage signal on high-voltage side to a voltage signal on low-voltage side, which is used in a power semiconductor device.
2. Description of the Background Art
In a HVIC (high voltage integrated circuit) on which, for example, an inverter, its driving circuit and its protection circuit are contained in a single chip, there is generally a detector for detecting voltage signals. This detector detects whether an abnormal voltage upsurge occurs in the respective switching elements on high-voltage side and low-voltage side of the half bridge of each phase.
FIG. 6 is a diagram illustrating an exemplary configuration of a power semiconductor device containing a circuit to detect whether an abnormal voltage upsurge occurs in a switching element on high-voltage side of a single-phase half bridge. On this circuit, for example, switching elements SW1 and SW2 such as IGBT (insulated gate bipolar transistor) are connected in series, and free wheel diodes D1 and D2 are subjected to inverse-parallel connection with the switching elements SW1 and SW2, respectively. These parts form a half bridge for one phase. The switching element SW1 on high-voltage side serves as a multi-emitter, to one output terminal of which one terminal of a shunt resistance SH is connected. By monitoring the value of voltage drop in the shunt resistance SH, it is detectable whether an abnormal voltage upsurge occurs in the switching element SW1. The other terminal of the shunt resistance SH is connected to a connection point MP of the switching elements SW1 and SW2.
An output signal of voltage drop in the shunt resistance SH is, for example, converted to a digital signal through an AD (from analog to digital) conversion circuit AD, and then inputted to a reverse level shift circuit IS. Hereat, the reverse level shift circuit IS functions to transfer a signal change of voltage drop (i.e., VIN-HGND) in the shunt resistance SH, while lowering its reference potential from potential HGND in the connection point MP to grounded potential GND that is a reference potential of other circuit.
The potential HGND at the connection point MP is high and in a float condition. For detecting output signals, it is therefore desirable that the reference potential is lowered to the grounded potential GND. Especially in the case of polyphase circuits such as three-phase circuit, one micro-processor in a HVIC detects an output signal of each phase and judges whether it is abnormal or not (e.g., it is judged abnormal when voltage upsurges in the shunt resistance exist in two phases). Hence, all the reference potentials of output signals should be lowered to the grounded potential GND, and it is for this reason that the reverse level shift circuit IS is present.
An output signal of the reverse level shift circuit IS (VOUT-GND) is inputted to an abnormality detection/stop signal output circuit DT equivalent to the above-mentioned microprocessor. On this circuit DT, it is detected whether there is an abnormal voltage drop at the shunt resistance SH in each phase, and if an abnormality is detected, a stop signal Sc for stopping the operation of the switching element SW1 is outputted.
The stop signal Sc is applied to a control electrode of the switching element SW1 via a level shift circuit LS and an output circuit OU. The level shift circuit LS functions to transfer the stop signal Sc while increasing its reference potential from the grounded potential GND to the potential HGND of the connection point MP. The output circuit OU functions to amplify the output of the level shift circuit LS.
In the forgoing description, it is not essential that an output signal of voltage drop at the shunt resistance SH be converted to a digital signal by the AD conversion circuit AD. For instance, if the reverse level shift circuit IS or abnormality detection/stop signal output circuit DT can process signals of analog input, the AD conversion circuit AD may be omitted so as to directly input a signal change of voltage drop to the reverse level shift circuit IS.
FIG. 7 is a diagram illustrating a conventional configuration of a reverse level shift circuit IS. On a reverse level shift circuit IS4, a high-side signal detecting circuit HD comprising a comparator etc. receives an input signal VIN and judges whether the value of voltage drop at a shunt resistance SH is greater than a predetermined value. When the former is larger than the latter, the high-side signal detecting circuit HD activates output.
The output of the high-side signal detecting circuit HD is applied via an inverter IV6 to the gate electrode of a Pch-DMOS (P-channel double diffusion metal oxide semiconductor) transistor PD1. When the output of the high-side signal detecting circuit HD is activated, the Pch-DMOS transistor PD1 enters operating state to flow current between its source and drain. Each circuit on the high-side is driven by a higher potential HVCC that a power source V1 generates from the potential HGND.
Since the Pch-DMOS transistor PD1 has high breakdown voltage and breakdown voltage characteristic of several hundreds volt level, it functions as a high-breakdown voltage resistance to perform reverse level shift of signals between the potential HVCC that is high and the grounded potential GND that is low. Current passing through the Pch-DMOS transistor PD1 flows to a resistance R5 on the low side, at which the current is converted to a voltage signal. A voltage drop at the resistance R5 is transferred to an inverter IV7 and an output circuit OT comprising an amplifier etc., and then outputted as an output signal VOUT. Each circuit on the low side is driven by a higher potential VCC that a power source V2 generates from the grounded potential GND.
Thus, the Pch-DMOS transistor PD1 is employed on the reverse level shift circuit IS4. From the viewpoint of voltage control between source and gate, in general, a Pch-transistor is employed on a reverse level shift circuit and a Nch-transistor is employed on a level shift circuit. Accordingly, when a level shift circuit and a reverse level shift circuit are allowed to coexist, it is necessary to form Nch- and Pch-DMOS transistors in a HVIC.
In manufacturing the DMOS transistors, however, it is difficult to form both of the Nch- and Pch-DMOS transistors in the HVIC, while adjusting characteristics, such as the threshold values of both transistors, to their respective desired values. It is especially difficult to form a Pch-DMOS transistor in a substrate at which a Nch-DMOS transistor is present. Hence, it is desired to configure a reverse level shift circuit without employing any Pch-DMOS transistor.
It can also be considered to configure a reverse level shift circuit using photocouplers, without using any DMOS transistor. However, the use of photocouplers increases the number of parts, which tends to raise the cost and results in poor reliability at high temperatures. From the standpoint of the entire arrangement, the configuration preferably contains a transistor that operates electrically.
According to a first aspect of the invention, a reverse level shift circuit that converts an input voltage signal using a first potential as a reference potential to an output voltage signal using a second potential lower than the first potential, as a reference potential, and then outputs the output voltage signal, comprises: a voltage-current conversion part operating based on the first potential, which converts the input voltage signal to a current signal corresponding to a value of the input voltage signal, then outputs the current signal; a Nch-MOS transistor having a source to which the second potential is applied via a load, a drain responsive to the current signal from the voltage-current conversion part, and a gate to which a fixed potential is applied; and a current-voltage conversion part operating based on the second potential, which converts current from the source of the Nch-MOS transistor to a voltage signal corresponding to a value of the current, and then outputs the voltage signal as the output voltage signal.
According to a second aspect of the invention, the reverse level shift circuit of the first aspect further comprises: a first current source operating based on the first potential, which outputs current corresponding to the current signal from the voltage-current conversion part, to the drain of the Nch-DMOS transistor; and a second current source operating based on the second potential, which contains the load and outputs a current signal corresponding to the current from the source of the Nch-MOS transistor, to the current-voltage conversion part.
According to a third aspect of the invention, the reverse level shift circuit of the second aspect is characterized in that the voltage-current conversion part contains a first resistance to which the input voltage signal is applied to generate the current signal; that the first current source contains a first current mirror circuit that receives the current signal from the voltage-current conversion part and outputs current corresponding to the current signal; that the second current source contains a second current mirror circuit serving as the load, which receives the current from the source of the Nch-MOS transistor and outputs a current signal corresponding to the current; and that the current-voltage conversion part contains a second resistance that receives the current signal from the second current source to cause a voltage drop for generating the output voltage signal.
According to a fourth aspect of the invention, the reverse level shift circuit of the third aspect is characterized in that the voltage-current conversion part further contains an operational amplifier having a negative input terminal and a positive input terminal to which the input voltage signal is applied, and a first transistor having (a) a first current electrode, (b) a second current electrode connected in common to the negative input terminal of the operational amplifier and one terminal of the first resistance, and (c) a control electrode to which output of the operational amplifier is applied, the first potential is applied to the other terminal of the first resistance; that in the current-voltage conversion part, a third potential higher than the second potential by a fixed value is applied to one terminal of the second resistance; that the first current mirror circuit comprises a second transistor having (d) a first current electrode connected to the first current electrode of the first transistor, (e) a second current electrode to which a fourth potential higher than the first potential by a fixed value, and (f) a control electrode connected to the first current electrode, and a third transistor having (g) a first current electrode connected to the drain of the Nch-MOS transistor, (h) a second current electrode to which the fourth potential is applied, and (i) a control electrode connected to the control electrode of the second transistor; and that the second current mirror circuit comprises a fourth transistor having (j) a first current electrode connected to the source of the Nch-MOS transistor, (k) a second current electrode to which the second potential is applied, and (l) a control electrode connected to the first current electrode, and a fifth transistor having (m) a first current electrode connected to the other terminal of the second resistance, (n) a second current electrode to which the second potential is applied, and (o) a control electrode connected to the control electrode of the fourth transistor.
According to a fifth aspect of the invention, the reverse level shift circuit of the third aspect is characterized in: that the second current source further contains a third current mirror circuit operating based on a third potential that is higher than the second potential by a fixed value, which receives a current signal from the second current mirror circuit and then outputs a current signal corresponding to the current signal, to one terminal of the second resistance of the current-voltage conversion part; and that the second potential is applied to the other terminal of the second resistance.
According to a sixth aspect of the invention, the reverse level shift circuit of the fifth aspect is characterized in that the voltage-current conversion part further contains an operational amplifier having a negative input terminal and a positive input terminal to which the input voltage signal is applied, and a first transistor having (a) a first current electrode, (b) a second current electrode connected in common to the negative input terminal of the operational amplifier and one terminal of the first resistance, and (c) a control electrode to which output of the operational amplifier is applied, the first potential is applied to the other terminal of the first resistance; that the first current mirror circuit comprises a second transistor having (d) a first current electrode connected to the first current electrode of the first transistor, (e) a second current electrode to which a fourth potential higher than the first potential by a fixed value, and (f) a control electrode connected to the first current electrode, and a third transistor having (g) a first current electrode connected to the drain of the Nch-MOS transistor, (h) a second current electrode to which the fourth potential is applied, and (i) a control electrode connected to the control electrode of the second transistor; that the second current mirror circuit comprises a fourth transistor having (j) a first current electrode connected to the source of the Nch-MOS transistor, (k) a second current electrode to which the second potential is applied, and (l) a control electrode connected to the first current electrode, and a fifth transistor having (m) a first current electrode, (n) a second current electrode to which the second potential is applied, and (o) a control electrode connected to the control electrode of the fourth transistor; that the third current mirror circuit comprises a sixth transistor having (p) a first current electrode connected to the first current electrode of the fifth transistor, (q) a second current electrode to which the third potential is applied, and (r) a control electrode connected to the first current electrode, and a seventh transistor having (s) a first current electrode, (t) a second current electrode to which the third potential is applied, and (u) a control electrode connected to the control electrode of the sixth transistor; and that in the current-voltage conversion part, the first current electrode of the seventh transistor is connected one terminal of the second resistance, and the second potential is applied to the other terminal of the second resistance.
According to a seventh aspect of the invention, the reverse level shift circuit of the first aspect is characterized in that the input voltage signal is PWM signal, and further comprising an integrating circuit that integrates the voltage signal from the current-voltage conversion part and outputs the result as the output voltage signal.
According to an eighth aspect of the invention, the reverse level shift circuit of the first aspect further comprises a signal output part that based on the input voltage signal, generates and outputs other output voltage signal using the first potential as a reference potential.
According to a ninth aspect of the invention, the reverse level shift circuit of the eighth aspect is characterized in that the signal output part contains an RS flip-flop that receives at its set input terminal the input voltage signal and outputs the mentioned other output voltage signal.
According to a tenth aspect of the invention, the reverse level shift circuit of the first aspect further comprises a control part that stops operation of the Nch-MOS transistor in accordance with a change in the output voltage signal from the current-voltage conversion part.
According to an eleventh aspect of the invention, the reverse level shift circuit of the tenth aspect is characterized in that the control part contains an RS flip-flop that receives at its set input terminal the output voltage signal from the current-voltage conversion part, and a switch that applies the second potential to the gate of the Nch-MOS transistor when output of the RS flip-flop is activated.
According to a twelfth aspect of the invention, a power semiconductor device comprises: a reverse level shift circuit according to the first aspect; switching elements on a high-voltage side and a low-voltage side connected in series; and a stop signal output circuit that receives the output voltage signal of the reverse level shift circuit and outputs a stop signal to stop operation of the switching element on high-voltage side, an output voltage of the switching element on the high-voltage side being used as the input voltage signal applied to the reverse level shift circuit.
In the first aspect of the invention, there is the Nch-MOS transistor having the source to which the second potential is applied via the load, the drain responsive to the current signal from the voltage-current conversion part, and the gate to which the fixed potential is applied. Since the Nch-MOS transistor is used in common gate construction, the value of the current gain between the drain and source is 1, so that the current signal from the voltage-current conversion part on the high side can be directly transferred to the current-voltage conversion part on the low side. This enables to configure a reverse level shift circuit by employing no Pch-DMOS transistor. Therefore, even when a level shift circuit and a reverse level shift circuit are allowed to coexist in a single HVIC, it is unnecessary to form any Pch-DMOS transistor in addition to a Nch-DMOS transistor, thereby making it easy to manufacture the HVIC.
In the second aspect of the invention, by the presence of the first and second power sources, the adverse effect on the output impedance of the voltage-current conversion part and the input impedance of the current-voltage conversion part can be lessened than the case of directly connecting the voltage-current conversion part and current-voltage conversion part to the Nch-MOS transistor. This results in the output voltage signal that faithfully reflects the change of input voltage signal.
In the third or fourth aspect of the invention, the voltage-current conversion part and current-voltage conversion part contain the resistances, and the first and second current sources contain the current mirror circuits. Therefore, a reverse level shift circuit can be configured easily by using these transistors and resistances.
In the fifth or sixth aspect of the invention, the second current source further contains the third current mirror circuit. The output of the third current mirror circuit is applied to one terminal of the second resistance of the current-voltage conversion part, and the second potential is applied to the other terminal of the second resistance. This provides an output voltage signal using the second potential as a reference potential.
In the seventh aspect of the invention, the input voltage signal is PWM signal, and the integrating circuit is added. Since the input voltage signal is a pulse string of which amplitude is constant, it is less susceptible to the influence of the channel length modulation effect of the Nch-MOS transistor. Therefore, it is possible to output an output voltage signal reflecting more faithfully the signal change prior to the PWM signal (the input voltage signal) modulation, by integrating on the integrating circuit a voltage signal from the current-voltage conversion part.
In the eighth or ninth aspect of the invention, the signal output part generates and outputs other output voltage signal using the first potential as a reference potential. Thereby, such other output voltage signal can be applied, as a control signal, to the circuit that operates using the first potential as a reference potential.
In the tenth or eleventh aspect of the invention, the control part stops the operation of the Nch-MOS transistor in accordance with a change of the output voltage signal from the current-voltage conversion part. Therefore, power consumption can be reduced by arranging such that the control part stops the current passing through the Nch-MOS transistor when it receives the change of the output voltage signal.
In the twelfth aspect of the invention, the stop signal output circuit stops the operation of the switching element on high-voltage side when it receives the output voltage signal of the reverse level shift circuit. This permits a power semiconductor device that is low in manufacturing cost and excellent in reliability.
It is an object of the present invention to provide a reverse level shift circuit that is low in cost and excellent in reliability by incorporating it into a driver IC (HVIC containing a level shift circuit), without using any Pch-DMOS transistor.
These and other objects, features, aspects and advantages of the present invention will become more apparent from the following detailed description of the present invention when taken in conjunction with the accompanying drawings.